SUB 20 -I2C mode (master/slave)

[pldcz]

Hello, we are writing application in vb .net, which communicates with i2c device once as a master and once as a slave in short time (miliseconds) .
When the SUB 20 works as a master we do not have problem, but when we switched to the SLAVE mode we are not able to recognize that the data transfer to the SLAVE was finished.
We found only one method ho to recognize the finished transfer to the SUB 20 (reading the FIFO buffer periodically).
Is it possible how to recognize the finished transfer in to the device(in I2c slave mode? for example some flag or some special bit ??? and we have next problem. How fast is possible to switch between mode SLAVE and MASTER, now we have problem if we use SUB20 as a I2C master and when we switched the SUB 20 to the SLAVE mode in shorter time than 6ms, the SUB20 is not able to read the correct I2c data.
May we ask you for some software sample (vb. net) ?
Could you help us.

Thank you very much

[xol]

Hello, we are writing application in vb .net, which communicates with i2c device once as a master and once as a slave in short time (miliseconds) .
When the SUB 20 works as a master we do not have problem, but when we switched to the SLAVE mode we are not able to recognize that the data transfer to the SLAVE was finished.
We found only one method ho to recognize the finished transfer to the SUB 20 (reading the FIFO buffer periodically).

Well this is the right way. What's wrong with it?

Is it possible how to recognize the finished transfer in to the device(in I2c slave mode? for example some flag or some special bit ??? and we have next

But to read this bit you will still have to read periodically bit status.

problem. How fast is possible to switch between mode SLAVE and MASTER, now we have problem if we use SUB20 as a I2C master and when we switched the SUB 20 to the SLAVE mode in shorter time than 6ms, the SUB20 is not able to read the correct I2c data.
May we ask you for some software sample (vb. net) ?
Could you help us.

Thank you very much

Theoretically where should be no problems with switching between master and slave.
You say SUB-20 can not read correct data, but can it read at all? And what's wrong with data.

Also what I2C master do you use? How this master knows that he can send data to SUB-20?
Tell me more about your whole system.

[pldcz]

Hello, thank you for your answer.

I will try to describe our system, it has three parts. SUB20 as a supervisor -I2C- unit IR PCB "master" -IR - unit IR PCB "SLAVE".

IR PCB (AT MEGA88PA-20MHz )
SUB 20 (VB. NET) FIFO (128 Byte) (I2C clock 50khz)
DATA packet on the I2C line 12 bytes


1.SUB 20 will send by I2C line data (as a I2C master ) to the IR PCB MASTER (as a I2C slave) / when the data transfer is done, SUB20 will be set up as a I2C slave T : 0ms
2.IR PCB MASTER received the data from SUB 20 T: 1ms
3.IR PCB MASTER has the required data (now is the IR PCB i2C Master) T: 2ms
4.IR PCB MASTER will send the data ( as a I2C master) to the SUB 20 T:2.1ms
5. The data transfer from IR PCB MASTER to the SUB20 is finished ( all bytes from IR PCB to SUB 20 were received with ACK, except the last one, of course). T:3.1 ms

So, when we checked the FIFO after above described operation the FIFO is sometimes empty or contains not correct DATA.
If, the response of the IR PCB Master will be delayed (+ 4ms ) step( 4) the data in the FIFO are correct. Our problem is that the DATA transfers on the I2c line are in the loop and
the max.time for the loop is 5 ms.

So our question is :

is it possible to create some "event" in the (vb.net) when the SUB20 is in the SLAVE MODE. the data from IR PCB MASTER just arrived ?.
Because, if we checking the FIFO periodically, we can not be sure, which data are inside of the FIFO. It means are the DATA in the FIFO the same as the DATA from the previous
check, or the new data just arrived ?

Correct timing for the using of FIFO.config( FIFO clear) ?

I hope that the description of our system and our problems is now clear?

Thank you

Regards

[xol]

Well at the first glance the main problem in your flow is switching time between SUB-20 master and SUB-20 slave.
It is not guaranteed that sub_fifo_config will do it in 2ms. The problem is not SUB-20 but USB itself. USB latency is around 1-2ms related to 1ms frame delay. Also consider that PC itself can delay API call as operating system can be busy at that moment (I assume you are running it on Windows PC that is by definition NON RELA TIME SYSTEM).
So to be on a safe side you have to
- Increase Slave to Master delay on IR PCB
or
- There is an option to rework SUB-20 FW to let it run in dual master/slave mode. In this case SUB-20 could perform master transactions and will reply to it's slave address. But this is not a simple and we need a good reason to do it.

[pldcz]

Ok, i understand.

Thank you